In memories which use address transition detection it is typical to have a separate address transition detector for each address signal for which transitions are to be detected. If any transition of the row address is to be detected, then a transition detector is commonly used for each row address signal. Each transition detector generates a pulse in response to a transition of the particular row address signal to which it corresponds. The outputs of these detectors are then summed to provide a single pulse which can be referred to as the summation of address transitions (SAT) pulse. This SAT pulse is then used to directly generate an equalization pulse which is used to equalize the bit lines upon its generation and to begin the sensing of data upon its termination. Although other signals, such as chip enable and write enable, may also be used in controlling the equalization pulse, the SAT pulse is the key pulse in the successful generation of the equalization pulse.
In the prior art, the summation function to generate the SAT pulse was achieved with a single, multiple-input NOR gate. The actual pulse generated by the large NOR gate is normally high and is pulsed to a logic low in response to an address transition so that the so generated is complementary to SAT and referred to as *SAT. The outputs of each of the transition detectors was connected to the inputs of this NOR gate. In the case of 7 row addresses typical for a 16K static random access memory (SRAM), this meant there were 7 transistors connected to a common output node for the *SAT pulse. This made this output node for the *SAT pulse highly capacitive. This is shown in FIG. 5 of U.S. Pat. No. 4,355,377, Sud et al. As SRAMs have reached higher densities such as 64K, the number of row addresses increased as well, raising the relative capacitance of the output node for the SAT pulse. The desire is for these transistors connected between the transition detectors and the output node to quickly pull down the output node to ground with the first edge of the signal provided by a transition detector. This has been difficult to achieve because the desire is also to quickly drive the output node to the power supply voltage to terminate the SAT pulse on the second edge of the signal provide by a transition detector. In order to drive the output node back up to or near the power supply voltage, a relatively large load device connected between the power supply and the output node was required. This limited the output swing on the output node and became related to the ratio of the gains of the load device and the pull-down transistors. The NOR gate was not ratioless. The gain for a single input was much less than unity gain. This is particularly undesirable because the desired fan-out for a SAT signal is quite large. If more than one load device was activated simultaneously, the output node was pulled closer to ground but this, of course, could not be relied upon. Because the pull-up is passive while the pull-up is passive, the relative timing of the pull-up and pull-down do not track with process variations. In those designs in which both row and column address transitions were detected the problems were even more severe because the wide NOR gate was extended across the whole chip, adding much capacitance and thus exacerbating the process tracking and gain problems.
To improve this situation, the load was clocked. In CMOS embodiments, the load device was a P channel transistor so that the output node could be brought to full power supply voltage with a clock signal that did not have to be bootstrapped. One clocking technique that was used was to use feedback from the equalization circuitry to turn the load device on and off. After the equalization circuitry received the *SAT pulse, the equalization circuit would output a feedback signal to enable the load device for termination of the *SAT signal. This was effective for the case in which there was only one address transition or all of the address transitions were simultaneous. The feedback was timed such that the feedback signal would not activate the load until at least the pulse from the activated transition detector was terminated. The load device was then turned on after the activated pull-down transistor or transistors was turned off. For the address skew case, however, the case in which the address transitions are not simultaneous but are separated in time, there arose a problem. The feedback signal would be generated in response to the first address transition so that the load transistor would be activated, but a second address transition would activate one of the pull-down transistors while the load was being activated by the feedback signal. This is the very situation to be avoided. The address transition detection performance was thus not asynchronous. Furthermore, the tracking issue remained a problem with this type of feedback reset of the *SAT node. For example, if transistors of shorter channel length were introduced into the process (which is often done to increase circuit speed), the feedback path could speed up more than the input to the NOR gate. This would cause the pulse width to get shorter and perhaps disappear altogether for some input conditions. This has been a typical problem in the design of self-resetting pulses and logic differentiators.
Another approach has been to clock the load using the transition detectors. This type of technique made the performance more nearly asynchronous, but did not not remove the basic problem of less than unity gain, non-tracking with process, and the problems associated with pulling down a large capacitance. It also made it necessary to run the reset signals across the chip.